Persistent State Machines: LLM Attention with INT4 In-Memory Cells

Persistent State Machines: Complete Mathematical Proofs and Vivado Implementation Synthesis (Version 8.0)

ABSTRACT We coming a general discrete model for attraction operators successful Large Language Models via Persistent State Machines (PSMs). Computation is broadcast to stationary in-memory cells that measure section deterministic authorities transitions. Complete mathematical proofs are fixed for quantization correction bounds, a actual multi-phase discrete Softmax building nether an definitive bounded-logits assumption, deterministic finite-automaton equivalence pinch spatial factorization, and rank successful DSPACE(O(n)).

We validate the implementation feasibility of the architecture connected modern programmable logic cloth done 2 chopped information flows:

1. Low-Power Evaluation (Zynq-7000 xc7z020): A afloat 1024-cell array (d=128) out-of-context (OOC) artifact creation implementation. By annotating the post-route netlist pinch a Switching Activity Interchange Format (SAIF) record obtained from a post-route functional simulation, we show that hardware-level self-activation gating restricts progressive move switching to sparse cells. The move powerfulness of the halfway logic is estimated beneath 1.0 mW, yielding a normalized move power of 3.81 × 10^-5 pJ/op.

2. System-on-Chip PCIe Integration (UltraScale+ xcvu9p): To verify system-level compatibility, a 256-cell sub-array (representing an integrated 1-head attraction system) is integrated wrong a afloat SoC. This includes AMBA AXI4 interconnects and an AMD Xilinx PCIe Gen3 x1 Bridge (XDMA v4.2). The complete SoC successfully closed timing astatine a unified strategy timepiece of 62.5 MHz (Worst Negative Slack WNS = +1.854 ns) nether the AWS Cloud FPGA Developer environment. The SoC occupies only 0.67% of the device's logic slices and 0.00% of DSP blocks, showing precocious scaling potential.

Functional simulation pinch much than 1 1000 random vectors confirmed bit-exact statement pinch a fixed-point package reference. All power figures are simulation-based instrumentality estimates for the synthesised logic; nary beingness FPGA committee measurement was performed, and system-level outer representation power is strictly excluded.

Japanese Patent Application No. 2026-177318 (Patent Pending)

029_Zenodo_ASMA_Paper_v8_0_FullProofMaster.pdf