CUDA is simply a elephantine for GPU compute, which includes instrumentality learning applications. So far, CUDA supports x86-64 and aarch64 CPUs. Now, Nvidia is looking astatine extending CUDA support to RISC-V. This move opens the doorway for RISC-V CPUs to provender GPU compute. Nvidia’s talk focuses connected the requirements that RISC-V CPUs must fulfill to activity pinch CUDA. Basically, they want a server-grade CPU and platform.
Nvidia starts by requiring a RVA23 CPU, and adherence to RISC-V’s server SoC and server platform specifications. Those specifications see RAS (reliability, availability, and serviceability) features, a specialized information processor, and different baseline features. Nvidia gets astir of their server-grade expectations fulfilled by those specifications.
Nvidia has a fewer much requirements that spell beyond the RISC-V floor plan aliases level specifications listed above, because they recovered it difficult to make CUDA package activity good without those features. They don’t want a lowest communal denominator problem, wherever they can’t usage performance-enhancing extensions because they can’t guarantee they’ll beryllium moving connected hardware pinch those extensions supported. From Nvidia’s perspective, that would unit them to vessel inefficient code. Nvidia brought up vector extensions arsenic an example, because predication support lets them debar branches.
ACPI is simply a much difficult requirement. ACPI lets package observe what hardware tin do, and tin beryllium utilized for power, performance, and thermal management. Nvidia’s package squad wasn’t happy because RISC-V hardware didn’t person ACPI erstwhile they started porting CUDA, but that business has been resolved. In 2025, the UEFI forum added RISC-V ACPI support. The RISC-V BRS (Boot and Runtime Services) specification was ratified past year, and includes ACPI.
Then, Nvidia requires PCIe coherency. Nvidia brings up a representation ordering problem wherever the CPU has written data, but that information is sitting successful a cache. If CUDA kicks disconnected a DMA petition to transcript that information to the GPU, the DMA engines whitethorn publication information from DRAM and miss modified information sitting successful CPU-side caches. When copying results backmost from the GPU, the CPU could publication old information from its caches aft the DMA engines constitute information to DRAM. Software would person to explicitly invalidate caches to debar that script if the strategy doesn’t person PCIe coherency. Working cache invalidations into the CUDA stack would beryllium difficult, and Nvidia considers PCIe coherency to beryllium a modular characteristic successful a server CPU. RISC-V’s server SoC specification recommends that hardware instrumentality cache coherency, but Nvidia wants a guarantee.
Nvidia besides wants hardware to support peer-to-peer PCIe communication. Without this capability, buffers copied betwixt 2 devices would person to spell done CPU memory, which costs capacity and summation complexity because it’ll request other synchronization signals.
Unfortunately, Nvidia didn’t spell complete each requirements successful detail. They noted that they’re aiming for a definite level of performance, and that the wide database fits wrong 2 pages. It’s an unfastened mobility whether it’s for illustration 2 double-spaced pages pinch ample font, aliases 2 statement pages allowed for an open-note exam (which a student will creatively capable pinch arsenic overmuch accusation arsenic possible).
Besides moving CUDA connected RISC-V CPUs, Nvidia concisely went complete requirements for NVLink Fusion. NVLink Fusion lets different companies instrumentality Nvidia’s NVLink IP connected their chips, letting them usage Nvidia’s NVLink C2C nexus pinch a civilization CPU of their choice. A hypothetical merchandise would activity overmuch for illustration Nvidia’s GB10, which linked Mediatek’s CPU dice pinch an Nvidia GPU utilizing NVLink C2C. Nvidia would of people want customers to usage Nvidia’s CPUs arsenic well. But if customers want to link civilization CPUs aliases different accelerators, Nvidia would still for illustration them to usage their NVLink IP. The civilization CPU could beryllium a RISC-V one.
NVLink Fusion’s requirements see each of CUDA’s requirements, on pinch whatever’s needed to support package frameworks for illustration DOCA and NCCL. Requirements widen to having a adjacent business pinch Nvidia, which sounds for illustration a given. Integrating IP tin beryllium a analyzable endeavor, and would apt require adjacent practice on the lines of Mediatek’s practice pinch Nvidia for GB10.
RISC-V’s package ecosystem has immoderate region to spell earlier catching up to x86-64 and aarch64. Nvidia’s effort to bring CUDA into the RISC-V world is simply a promising development. Unfortunately, those efforts don’t needfully mean you tin connect a Nvidia GPU to a RISC-V strategy and get cracking pinch CUDA. The immense mostly of existing RISC-V hardware won’t meet Nvidia’s requirements. In fact, I would beryllium amazed if immoderate RISC-V user hardware meets those requirements successful the adjacent future. ACPI is an evident sticking point, and seems difficult for vendors to prime up. In the aarch64 world, ACPI support has been spotty astatine champion moreover though it has been in standards for years. A RISC-V modular ratified successful 2025 would apt return respective years to get wide support, if not more.
When and if RISC-V systems commencement showing up pinch CUDA support, they’ll apt beryllium server systems alternatively than the azygous committee computers hobbyists tin afford. Nvidia noted that they’re partnering pinch SiFive, and SiFive plans to demo a strategy moving CUDA astatine Hot Chips. Nvidia implied the illustration CPU specifications connected their descent correspond to that system, and those specifications propose it’s a precocious halfway count server chip. I look guardant to seeing that, but I besides dream Nvidia doesn’t artifact CUDA from moving connected unsupported systems. I would emotion to spot enthusiasts return a changeable astatine feeding Nvidia GPUs from RISC-V systems.
Going forward, I dream Nvidia tin relax their requirements to springiness existing RISC-V systems a amended chance of gathering them. Lack of vector extensions aliases PCIe coherency doesn’t needfully lead to intractable capacity problems. Using branches alternatively of predication tin activity good if those branches are predictable, which they often are. Cache invalidations required to activity astir deficiency of PCIe coherency will incur a capacity cost. However, that costs whitethorn beryllium acceptable for workloads that do a batch of compute compared to information movement. The aforesaid applies to PCIe peer-to-peer transfers. It’s awesome to person things spell fast, but things that don’t hap often tin beryllium put connected a slow way if you’re careful. Hopefully, Nvidia’s existent requirements stem from expedience, and were group to let a fast, low-risk RISC-V port. And hopefully, CUDA evolves successful a measurement that makes it accessible to a wide scope RISC-V systems, not conscionable specialized endeavor designs.
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